The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also lead to high-k dielectric layers and conductive (e.g., metal) layers being adopted to form gate stacks in various IC devices, such as metal-oxide-semiconductor field-effect-transistors (MOSFETs). The conductive layers are often tuned to have a proper work function to achieve a designed threshold voltage for n-type and p-type devices. Currently, the conductive layers are patterned using an etching process, for example, a dry etching process or a wet etching process. However, it has been observed that a dry etching process results in damage to the high-k dielectric and conductive layers, and sometimes, leaves photoresist residue; and a wet etching process often results in lateral etching, degrading patterning profiles.
Accordingly, what is needed is a method for making an IC device that addresses the above stated issues.